FLIP FLOP

Also referred to as a bistable gate, a type of circuit that is interconnected with like circuits to form logic gates in digital integrated circuits, such as memory chips and microprocessors. The name “flip-flop” comes from the circuit’s nature of alternating between two states when a current is applied to the circuit (for example, 1 to 0 or 0 to 1). A flip-flop will maintain its state indefinitely until it receives an input pulse, called a trigger, which forces it to alternate its state. Once the circuit changes state it remains in that state until another trigger is received.

SR Flip-Flop

An SR Flip Flop is an arrangements of logic gates that maintains a stable output even after the inputs are turned off.  This simple flip flop circuit has a set input (S) and a reset input (R). The set input causes the output of 0 (top output) and 1 (bottom output).  The reset input causes the opposite to happen (top = 1, bottom =0).  Once the outputs are established, the wiring of the circuit is maintained until S or R go high, or power is turned of to the circuit.

D-Flip-Flop

The edge-triggered D flip-flop is easily derived from its RS counterpart. The only requirement is to replace the R input with an inverted version of the S input, which thereby becomes D. This is only needed in the master latch section; the slave remains unchanged.

One essential point about the D flip-flop is that when the clock input falls to logic 0 and the outputs can change state, the Q output always takes on the state of the D input at the moment of the clock edge. This was not true of the RS and JK flip-flops. The RS master section would repeatedly change states to match the input signals while the clock line is logic 1, and the Q output would reflect whichever input most recently received an active signal. The JK master section would receive and hold an input to tell it to change state, and never change that state until the next cycle of the clock. This behavior is not possible with a D flip-flop.

JK Flip Flop

To prevent any possibility of a "race" condition occurring when both the S and R inputs are at logic 1 when the CLK input falls from logic 1 to logic 0, we must somehow prevent one of those inputs from having an effect on the master latch in the circuit. At the same time, we still want the flip-flop to be able to change state on each falling edge of the CLK input, if the input logic signals call for this. Therefore, the S or R input to be disabled depends on the current state of the slave latch outputs.

If the Q output is a logic 1 (the flip-flop is in the "Set" state), the S input can't make it any more set than it already is. Therefore, we can disable the S input without disabling the flip-flop under these conditions. In the same way, if the Q output is logic 0 (the flip-flop is Reset), the R input can be disabled without causing any harm. If we can accomplish this without too much trouble, we will have solved the problem of the "race" condition